Title: Dynamically reconfigurable neuron architecture for the implementation of self-organising learning array

Authors: Janusz A. Starzyk, Yongtao Guo, Zhineng Zhu

Addresses: School of Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701, USA. ' School of Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701, USA. ' School of Electrical Engineering and Computer Science, Ohio University, Athens, OH 45701, USA

Abstract: In this paper, we describe a new dynamically reconfigurable neuron hardware architecture based on the modified Xilinx Picoblaze microcontroller and self-organising learning array (SOLAR) algorithm reported earlier. This architecture is aiming at using hundreds of traditional reconfigurable field programmable gate arrays (FPGAs) to build the SOLAR learning machine. SOLAR has many advantages over the traditional neural network hardware implementation. Neurons are optimised for area and speed, and the whole system is dynamically self-reconfigurable during the runtime. The system architecture is expandable to a large multiple-chip system.

Keywords: reconfigurable architectures; dynamic reconfiguration; FPGA; field programmable gate arrays; machine learning; neural networks; picoblaze; neuron architecture; self-organising learning array.

DOI: 10.1504/IJES.2006.010168

International Journal of Embedded Systems, 2006 Vol.2 No.1/2, pp.95 - 105

Published online: 05 Jul 2006 *

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