Title: System-level parallelism and concurrency maximisation in reconfigurable computing applications
Authors: Esam El-Araby, Mohamed Taher, Kris Gaj, Tarek El-Ghazawi, David Caliga,Nikitas Alexandridis
Addresses: Department of Electrical and Computer Engineering, The George Washington University, 801 22nd Street NW, Washington DC 20052, USA. ' Department of Electrical and Computer Engineering, The George Washington University, 801 22nd Street NW, Washington DC 20052, USA. ' Electrical and Computer Engineering Department, George Mason University, 4400 University Drive, Fairfax, VA 22030, USA. ' Department of Electrical and Computer Engineering, The George Washington University, 801 22nd Street NW, Washington DC 20052, USA. ' SRC Computers, Inc., 4240 North Nevada Avenue, Colorado Springs, CO 80907, USA. ' Department of Electrical and Computer Engineering, The George Washington University, 801 22nd Street NW, Washington DC 20052, USA
Abstract: Reconfigurable computers can leverage the synergism between conventional processors and FPGAs to provide both hardware functionalities and general-purpose computers flexibility. In a large class of applications on these platforms, the data-transfer overheads can be comparable or even greater than the useful computations which can degrade the overall performance. In this paper, we perform a theoretical and experimental study of this specific limitation. The mathematical formulation of the problem has been experimentally verified on the state-of-the-art reconfigurable platform, SRC-6E. We demonstrate and quantify the possible solution to this problem that exploits the system-level parallelism within reconfigurable machines.
Keywords: reconfigurable computers; field programmable gate arrays; FPGA; direct memory access; DMA; reconfigurable architectures; system-level parallelism; concurrency maximisation.
International Journal of Embedded Systems, 2006 Vol.2 No.1/2, pp.62 - 72
Published online: 05 Jul 2006 *
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