Title: Parallel video processing on FPGA architecture

Authors: Lamjed Touil; Abdessalem Ben Abdelali; Lilia Kechiche; Chiheb Chaieb; Bouraoui Ouni; Abdellatif Mtibaa

Addresses: Networked Objects Control and Communications Systems Laboratory, ENISo, and Higher Institute of Applied Sciences and Technology of Sousse, University of Sousse, Tunisia ' Laboratory of Electronics and Microelectronics, University of Monastir, Tunisia ' Laboratory of Electronics and Microelectronics, University of Monastir, Tunisia ' Higher Institute of Applied Sciences and Technology of Sousse, University of Sousse, Tunisia ' Networked Objects Control and Communications Systems Laboratory, ENISo, University of Sousse, Tunisia ' Laboratory of Electronics and Microelectronics, University of Monastir, Tunisia

Abstract: Real-time video applications are becoming widely used in many domains with more demand for high performance. Video processing is intensive and habitually has accompanying real-time or super-real-time requirements. Such us, multiple cameras are used in monitoring and surveillance systems in automatically real-time analyse video to detect unusual events. Due to the strong computational imposed by video algorithms, real-time video treatment is notably amenable to concurrent processing. Classical implementation solutions whether based on general purpose processors or dedicated ones like DSP cannot fulfil wanted performance. In this article, we focus on the applicability of computing reconfigurable architectures to parallel video processing applications. The experiment results show that the proposed hardware-oriented multi-treatment architecture can provide an average frame rate of 45 frames/s at high definition resolution. Statistics show a consumption about 18% of logic resources and 27% of on chip memory which gives the possibility to integrate additional treatments.

Keywords: FPGA; multi-port memory controller; MPMC; video processing; cut detection; picture in picture.

DOI: 10.1504/IJHPSA.2018.100716

International Journal of High Performance Systems Architecture, 2018 Vol.8 No.3, pp.169 - 178

Accepted: 29 Nov 2018
Published online: 16 Jul 2019 *

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