A soft error tolerant register file for highly reliable microprocessor design Online publication date: Wed, 02-May-2018
by Nastaran Rajaei; Ramin Rajaei; Mahmoud Tabandeh
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 7, No. 3, 2017
Abstract: Dealing with radiation-induced soft errors is of the main design challenges in today's nanometer design of embedded systems especially in safety critical applications. Register file is a vulnerable section of a microprocessor that needs to be protected against soft errors. This paper proposes a soft error tolerant structure for the register file of the safety-critical embedded processors. In this structure, the double modular redundancy (DMR) technique based on a new hardware implementation is employed for the normal values. Moreover, the unused bits of the registers are used to be further redundant for the used ones for the narrow-width values. We show that the proposed structure offers much more reliability improvement in comparison with the conventional techniques for protection of register files such as DMR, triple modular redundancy and error detection and correction solutions based on Hamming code.
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