Area-efficient floorplans and interconnects for homogeneous multi-core architectures
by Fadi N. Sibai
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 1, No. 3, 2008

Abstract: Homogeneous multi-core architectures come in a variety of floorplans. A large portion of the chip area is occupied by the second level cache memories and the interconnect. Usually, the floorplan is dictated by the interconnect type and the second level cache memory size and by whether large resources on the chip are shared or private. We consider floorplans for a 16-core architecture consisting of identical cores and estimate their areas based on two different processor cores. Then, we focus on an area-efficient and performance-scaling four-partition crossbar-interconnected architecture with third level cache memory and conduct performance modelling and evaluation of the multi-core architecture's memory system. With a database workload and a first level cache miss rate under 20%, the Average Memory Access Time (AMAT) is estimated to be under 20 processor cycles. With higher memory contention resulting into longer bridge queue wait times, the various cache miss rates rate make a more pronounced effect on the Chip Multiprocessors AMAT, necessitating design measures like proper cache sizing. When the size of shared resources becomes too large, recent work in sharing and partitioning large resources in CMP architectures becomes crucial.

Online publication date: Thu, 04-Dec-2008

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