Fine grain pipeline systems for real-time motion and stereo-vision computation Online publication date: Thu, 19-Apr-2007
by Javier Diaz, Eduardo Ros, Alberto Prieto, Francisco J. Pelayo
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 1, No. 1, 2007
Abstract: Image processing systems require high computational load that motivates the design of specific hardware architectures in order to arrive at real-time platforms. We adopt innovative design techniques based on the intensive utilisation of the inherent parallelism available on devices based on reconfigurable hardware. We customise fine-grain pipelining and superscalar units to implement specific computing architectures for motion and stereo-vision computing circuits. This high parallelism level allows us to achieve a high data throughput (one pixel feature estimation per clock cycle). This paper extensively uses these techniques for designing high performance image processing systems which fit early cognitive vision models specifications. Furthermore, it highlights the necessity of on-chip integration mechanisms, since the data throughput (bandwidth requirements) of the full system requires a very large bandwidth.
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