Optimisation of total harmonic distortion using carrier-based PWM techniques for nested multilevel inverter topologies Online publication date: Thu, 10-Jun-2021
by Narendra Kumar Muthukuri; Rajanand Patnaik Narasipuram; Subbarao Mopidevi
International Journal of Industrial Electronics and Drives (IJIED), Vol. 5, No. 2, 2020
Abstract: This paper presents the design and simulation of multilevel inverter topologies configuring nested arrangement. It has the remarkable feature of reduced number of diodes and concomitantly higher efficiency compared to the neutral-point clamped (NPC) inverter topology. The simulation of nested multilevel topology is fulfilled for four, five, six, seven, eight and nine output voltage levels having connected with a three phase star connected RL load. The performance comparison for different output voltage levels is accomplished in terms of total harmonic distortion (THD). The carrier-based sinusoidal PWM techniques, namely, phase disposition (PD), phase opposition disposition (POD) and alternative phase opposition disposition (APOD) are adopted here in order to reduce harmonic distortion in the output voltage as well as load current. The harmonic analysis is carried out through FFT analysis. The simulation is performed using MATLAB/Simulink software version R2012b.
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