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International Journal of High Performance Systems Architecture (IJHPSA)

Title Author(s) Vol. and Issue nos. Page nos. Full-text article
Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagramsJ.P. Anita; P. SudheeshVol.6 No.151-60Free access
Slider: an online and active deadlock avoider by serial execution of critical sectionsZhen Yu; Xiaohong Su; Peijun MaVol.6 No.136-50Free access
Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs Burhan Khurshid; Roohie NaazVol.6 No.128-35Free access
KUMMS: optimising DRAM locality with Kernel-user behavioursBeilei Sun; Xi Li; Chao Wang; Bo Wan; Xuehai ZhouVol.6 No.113-27Free access
On the effectiveness of accelerating MapReduce functions using the Xilinx Vivado HLS toolMageda Sharafeddin; Mazen A.R. Saghir; Haitham Akkary; Hassan Artail; Hazem HajjVol.6 No.11-12Free access