Forthcoming articles

 


International Journal of High Performance Systems Architecture

 

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International Journal of High Performance Systems Architecture (8 papers in press)

 

Regular Issues

 

  • A VLSI Architecture of CORDIC based Popular Windows and Its FPGA Prototype   Order a copy of this article
    by VIKAS KUMAR, Kailash Chandra Ray, Preetam Kumar 
    Abstract: Popular window technique such as Hamming, Hanning, Blackman, Blackman - Harris and Flat Top windows are an obvious choice before Fast Fourier Transform(FFT) in the domain of signal processing, communication system and image processing to minimize the undesirable phenomenon i.e. spectral leakage and picket fence effect arise due to direct truncation by rectangular window. As the window characteristics depends upon the type of the function and length of window used, hence this is necessary to choose a particular window function and window length depending upon the applications. In other hand, real time implementation of window function demands efficient and flexible VLSI architecture. Hence this paper presents a new hardware efficient CORDIC based VLSI architecture which is capable of reconfigurability to choose a window function among aforesaid popular window functions and window length ranging from 8 to 32K, depending upon the application. Further this proposed architecture is prototyped on FPGA for real time validation and implementation results have been highlighted along with error analysis.
    Keywords: CORDIC; Flat Top Window; Blackman-Harris Window; Blackman Window; Hamming Window; Hanning Window; FFT; FPGA; Signal Processing.ORDIC; Flat Top Window; Blackman-Harris Window; Blackman Window; Hamming Window; Hanning Window; FFT; FPGA; Signal Processing.C.

  • Synthesis of Standard Functions and Generic Ex-OR Module using Layered T Gate   Order a copy of this article
    by Chiradeep Mukherjee, Saradindu Panda, Asish Kr Mukhopadhyay, Bansibadan Maji 
    Abstract: The Quantum-dot Cellular Automata (QCA) which is the most promising technology in the paradigm of Nano electronics has already been claimed to possess ultra-high packing density, high clocking speed and extremely low power dissipation. In the last year with the advancement of successful instantiation of QCA, it proves proper functionality even in room temperature. The previous logic reduction schemes of QCA have made multi-level complex digital design simpler. Still their exist lack of optimal design of generic Exclusive OR Gate design in this field. This work proposes a novel design of high fan-in Exclusive-OR Gate by using the Layered T Gate of QCA. The Robustness Analysis of Layered T Gate has also been done to focus the advantage of Layered T Architecture in generic sense considering the defects of QCA. The Layered T architecture is implemented in standard function realization to verify the scalable and reusable nature of Layered T module. The impacts of device-fabrication metrics such as Layer Separation, Radius of Effect, Cell Spacing and AUF on Layered T Gate are thoroughly investigated. Based on AUF analysis of different QCA logic gates, the proper logic reduction technique for complex digital circuit is proposed. The synthesis of Three-Literal Standard Functions by using Layered T Gate reports an average 29.31% less area requirement as compared to the best reported design so far. Primarily two-input Layered T Exclusive OR shows 18.75% less Cell Requirement and 6.20% less area requirement as compared to the conventional two-input Exclusive OR Designs. An important QCA Circuit Design metric Costα is also calculated for QCA Exclusive OR Designs. The analysis shows 36.37% improvement in Costα with respect to the best reported Exclusive OR design so far. Finally, two-input Layered T Exclusive OR Module extends its design methodology to implement high fan-in Exclusive OR Gate designs with proper formulation of O-Cost and delay in QCA.
    Keywords: QCA; Area Utilization Factor; O-Cost; Layered T Gate; Defects of QCA; Standard Function; Exclusive OR Gate; QCADesigner.

  • An Enhanced Model for Reliable Deflection Routing in Mesh Network On Chip   Order a copy of this article
    by Simi Zerine Sleeba, M.G. Mini 
    Abstract: Massive integration of processing cores into a finite chip area increases the possibility of damage and failure of various chip components. Issues and solutions related to reliable on-chip communication is of great importance in this context. On-chip routers play a vital role in routing packets through the NoC. In this paper, we propose a new fault tolerant routing model for NoCs using deflection routing mechanism. This model intelligently utilizes fault-free unidirectional links between the routers to forward flits to their destinations in few number of hops. These links are activated at regular time intervals so that they serve as alternate productive paths for flits which are delayed due to faults in their computed routes. We also present a routing algorithm that exploits the path diversity in the network generated by the enhanced model. From experimental analysis, we obtain significant improvement in the network performance parameters like flit latency, deflection rate and dynamic energy dissipation across router links for the proposed model compared to the state-of-the-art fault tolerant routing methods in NoC.
    Keywords: Network on Chip; Fault tolerant routing; Deflection routing; Average latency; Dynamic link energy.

  • Partial Dynamic Reconfiguration Framework for FPGAs through Remote Access   Order a copy of this article
    by Anitha Arumalla, Madhavi Latha Makkena 
    Abstract: With the advent of Internet of Things (IoT) and Ubiquitous computing, the need for resource aware reconfiguration platform is increasing tremendously. Though a number of dynamic partial reconfiguration systems are available, they consume a significant portion of base system area in comparison with the application running on the system. Larger area requirements of reconfigurable platform cannot take the advantage of reconfigurable systems. Hence a light weighted and flexible reconfigurable framework with remote access reconfiguration is proposed. The system occupied less than 1% of the total device resources and attained 400MBps reconfiguration throughput. This framework can be used to any number of reconfiguration regions and is suitable for any application. The proposed framework for partial dynamic reconfiguration through remote access is tested on Virtex5 XC5VFX70T and Virtex6 XC6VLX240T FPGAs with 1Gbps Ethernet link.
    Keywords: dynamic partial reconfiguration; ICAP controller; remote access.

  • Capacity Planning of the Registration Server in Cloud Storage   Order a copy of this article
    by Rui Gu, Shunfu Jin, Haixing Wu 
    Abstract: Cloud storage is one of the key services in cloud computing. In order to appeal more users to the cloud storage, free cloud experience is provided to potential users. A registration server is set specially for intentional users who are satisfied with the free experience and want to register as VIPs (Very Important Persons). In order to mathematically evaluate the system performance and optimally plan the registration server, we establish a queueing network based system model. We analyze the steady-state distribution of the system model and derive the performance measures of the system in terms of the average response time of potential users and the utilization of registration server. For balancing different performance measures, we establish a cost function and develop an optimization algorithm to plan the capacity of the registration server with a reasonable service rate.
    Keywords: cloud storage; registration; capacity planning; queueing network; optimization algorithm.

  • A Soft Error Tolerant Register File for Highly Reliable Microprocessor Design   Order a copy of this article
    by Nastaran Rajaei, Ramin Rajaei, Mahmoud Tabandeh 
    Abstract: Dealing with radiation-induced soft errors is of the main design challenges in todays nanometer design of embedded systems especially in safety critical applications. Register file is a vulnerable section of a microprocessor that needs to be protected against soft errors. This paper proposes a soft error tolerant structure for the register file of the safety-critical embedded processors. In this structure, the double modular redundancy (DMR) technique based on a new hardware implementation is employed for the normal values. Moreover, the unused bits of the registers are used to be further redundant for the used ones for the narrow-width values. We show that the proposed structure offers much more reliability improvement in comparison with the conventional techniques for protection of register files such as DMR, triple modular redundancy and error detection and correction solutions based on Hamming code.
    Keywords: Double Modular Redundancy (DMR); Triple Modular Redundancy (TMR); Register File; Single Event Upset (SEU); Soft Error.

  • An exclusive cache replacement policy based on read priority and dynamic sliding   Order a copy of this article
    by Debabala Swain, Banchhanidhi Dash 
    Abstract: The conventional cache replacement algorithms have massive hardware cost with ambiguous logic and measurability. Increasing the cache levels do not give a better solution for the hardware complexity and performance issues in multi-core processors.Rather number of read misses on executing the complex memory intensive program can increase the execution time in multi-core processors. This paper proposes a new way of cache replacement policy Weight based Read Priority Replacement (WRPR), which works on the read priority of a cache line in all levels of cache. By making it read prior instead of write, the cache lines with more read access are highly weighted. During replacement, the cache eviction is done from dynamic logical cache regions based on its weight. The algorithm performance is tested using multi-core cache simulator with different benchmark workloads in the SMPCache simulator. The proposed replacement policy can work on any exclusive cache level in a multi-level hierarchy. It shows an improved performance from the hit rate context.
    Keywords: Exclusive cache; read priority; dynamic sliding; multi-core; multi-level hierarchy; WRPR.

Special Issue on: Internet of Things Principles, Methodologies, and Applications

  • A New Ontology Ranking Method with OntoDUIA for Ontology Retrieval System   Order a copy of this article
    by Jianghua Li, Boyu Li 
    Abstract: Ontology is being widely used for data integration and knowledge discovery in the field of data engineering. Ontology ranking is one of the important function of ontology search engine, which ranks the searched ontologies in a reasonable order. A good ranking method can help a user acquiring the satisfied ontology efficiently from a considerable amount of search results. However, existing methods in literatures are unable to rank ontologies to well meet users ranking demand due to their inherent shortcomings. In this paper, a novel ontology ranking method OntoDUIA is proposed and presented. It evaluates user-query related ontologies and ranks them based on a set of metrics of query relevance, usability, instance distribution and authority of ontology. To evaluate OntoDUIA, a series of experiments are conducted to compare the performance among OntoDUIA and some existing ontology ranking methods as well as human experts. Experimental results show that OntoDUIA can effectively meet users ontology ranking demand, and it achieves stable and reliable ranking results. Finally, OntoDUIA can also be applied to ontology retrieval system.
    Keywords: Ontology ranking; Relevance metrics; Usability quality metrics; Instance metrics.