Forthcoming and Online First Articles

International Journal of High Performance Systems Architecture

International Journal of High Performance Systems Architecture (IJHPSA)

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International Journal of High Performance Systems Architecture (5 papers in press)

Regular Issues

  • Analysis of Area and Energy Efficiency in Fruit-v2, Fruit-80, Grain128AEAD for resource constrained devices   Order a copy of this article
    by Dheeraj Kumar Sharma  
    Abstract: There is a lot of increase in technology. As there are restrictions on resources available, there is a need to implement lightweight stream ciphers. The ciphers are used for the encryption of data. So, the security of data is also an important factor. As handheld devices are increasing, the need for energy-efficient devices became more vital. Keeping all these requirements in mind, researchers have made much research on ciphers. Unrolling in stream ciphers showed the energy-efficient way to implement ciphers. In this paper, the unrolling in Fruit-v2, Fruit-80, and Grain128AEAD stream ciphers is discussed. Using Xilinx ISE Design Suite and Verilog HDL, simulation is performed for different unrolling factors. Using Synopsys DC compiler, power and energy are calculated. The unrolling round for which the energy is optimized for Fruit-v2, Fruit-80 and Grain128AEAD are 16, 16, and 64 respectively. This paper discusses area, power and energy consumption.
    Keywords: Unrolling; stream cipher; lightweight cryptography; energy efficiency; resource constrained devices.
    DOI: 10.1504/IJHPSA.2023.10058380
     
  • A chaotic genetic algorithm with polynomial mutation for warehouse robot path planning   Order a copy of this article
    by Ling Lin, Jiangtao Xu, Weijun Gao, Xianjie Peng, Chengming Yang 
    Abstract: To plan efficient picking path for warehouse robots, a chaotic genetic algorithm with polynomial mutation is recommended in this paper. First, in order to improve the efficiency of the genetic algorithm, the chaotic theory is employed to design a population initialization strategy, which can increase the diversity of the initial population. Second, on the basis of the mutation operator designed based on polynomial mutation, the algorithm’s capacity for diversity preservation can be enhanced. Third, two novel adaptive adjustments are presented for crossover and mutation operations in order to achieve a balance between convergence and diversity. As assessment indices of the fitness function, the path length, turn timings, and running energy consumption of the robot are taken into considerations. Simulation results indicate that the suggested approach outperforms the basic genetic algorithmand the ant colony optimization algorithm in terms of path length and energy consumption.
    Keywords: Warehouse Robots; Genetic Algorithm; Diversity; Energy Consumption.
    DOI: 10.1504/IJHPSA.2023.10059830
     
  • Optimized Architectures of Midori Block Cipher for Area Constrained IoT Applications   Order a copy of this article
    by Aakanksha Baghel, Zeesha Mishra, Onika Parmar, Amit Singh Rajput 
    Abstract: Over the past few year, Lightweight Cryptography has been recognised as top-notch for gratifying the requirements of resource constrained environments (RCE) for Internet of Things (IoT) applications. For several RCE applications, a range of light-weight cryptographic methods have been put forth. In this paper, Midori lightweight block cipher has been area optimised using unconventional serial architectures and memory address scheduling technique. This paper suggests two serial architectures for area optimisation of 64-bit and 128-bit block sizes respectively. The proposed designs are implemented in verilog hardware description language (HDL) using Xilinx ISE Design suite. Fair comparison of the proposed designs has been done on different families of field programmable gate array (FPGA). The proposed design has shown a percentage improvement of 22.03% and 15.28% in terms of area for 64-bit and 128-bit block size respectively. Similarly, the percentage improvement for throughput is 21.43% and 15.65% and for 64 and 128-bit block size respectively on FPGA Virtex-5platform.
    Keywords: IoT; FPGA; RCE; Throughput; SPN structure; Cryptography; Midori; Slices.
    DOI: 10.1504/IJHPSA.2023.10060964
     
  • Research on load prediction of Back Propagation neural network based on genetic algorithms   Order a copy of this article
    by Lei Yan, GuoXing Mu, Qibing Wang, Zhifang He, Yanfang Zhu 
    Abstract: To address the problem that back propagation (BP) neural networks are prone to overfitting and falling into local optimality, resulting in low accuracy of electricity load forecasting, this paper proposes a method for electricity load forecasting based on an improved genetic algorithm (GA) and the BP neural network. Through modelling and analysis of load data, better root mean square error (RMSE) and mean absolute percentage error (MAPE) are obtained compared with the traditional BP neural networks, proving the methods superiority.
    Keywords: Electricity market; GA;Market clearing; Load forecasting; BP.
    DOI: 10.1504/IJHPSA.2023.10062409
     
  • Efficient Low Area High Frequency Hardware Implementations of Shadow Lightweight Block Ciphers for Resource-Constrained IoT Devices and Sensor Networks   Order a copy of this article
    by G. Krishna Pranav, Zeesha Mishra, Bibhudendra Acharya, Bijayananda Patnaik 
    Abstract: As a result of technology advancement modern applications need optimized requirements like low area, low power and low cost etc., Cryptography fails to meet the above limited resource criteria, which laid a path for lightweight cryptography as it deals with modern limited resource issues very efficiently. This paper deals with Lightweight Shadow block cipher whose encryption is based on generalized Feistel structure. To optimise the performance i.e., by improving the throughput and frequency of the algorithm, A 4-Clock Loop Unrolled architecture (S1) of Shadow-32 and Pipelined architecture of Shadow-64 (S2) are proposed. They are simulated and implemented on the various boards of Spartan and Virtex FPGA families and their performance metrics are compared to various lightweight block ciphers and have observed a best improvement of 365.6% and 140% in the throughput than the conventional architectures in S1 and S2 respectively.
    Keywords: IoT; Cryptography; Shadow; Encryption; Lightweight Cryptography; Field Programmable Gate Array (FPGA).
    DOI: 10.1504/IJHPSA.2023.10062460