Forthcoming articles

 


International Journal of High Performance Systems Architecture

 

These articles have been peer-reviewed and accepted for publication in IJHPSA, but are pending final changes, are not yet published and may not appear here in their final order of publication until they are assigned to issues. Therefore, the content conforms to our standards but the presentation (e.g. typesetting and proof-reading) is not necessarily up to the Inderscience standard. Additionally, titles, authors, abstracts and keywords may change before publication. Articles will not be published until the final proofs are validated by their authors.

 

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International Journal of High Performance Systems Architecture (5 papers in press)

 

Regular Issues

 

  • Soft Skills Requirements in Mobile Applications Development Employment Market   Order a copy of this article
    by JIngdong Jia, Zupeng Chen, Xi Liu 
    Abstract: The soft skills of developers have a major influence on the quality of software product and project. However, which soft skills are important for mobile applications development remains unknown. Additionally, it is necessary to examine the differences of soft skills requirements between traditional software and mobile applications development. In this article, based on text mining including word segmentation, similarity calculation and clustering analysis, we analyse lots of advertisements, and extract 13 categories of soft skills requirements for mobile applications development. We also compare the categories with those for traditional software development. We find that communication and teamwork are still the most important two soft skills. However, fast learning is more important for mobile developers, and we identified four soft skills that are not proposed before. Additionally, season has a minor impact on soft skills requirements of mobile applications development.
    Keywords: soft skill; mobile application development; job advertisement; text mining; cluster analysis.

  • Energy Optimized Cryptography (EOC)for Low Power Devices in Internet of Things   Order a copy of this article
    by RAJESH G, Vamsi Krishna C, Christopher Selvaraj B, Roshan Karthik S, Arun Kumar Sangaiah 
    Abstract: Internet of Things(IoT) has a plethora of devices ranging from high capacity servers to low powered devices that works with Bluetooth, ZigBee, GPRS, RFID and WiFi etc,. These the low power devices are constrained to security, power management, reliability and privacy limitations. The existing traditional security algorithms could not be applied to these low power devices, due tothe high processing and battery power requirements. Here proposed an Energy Optimized Cryptography (EOC) for low power devices in IoT. Here the security of the low power devices are providedby two light weight security techniques called R2CV, a sub key generation method and Optimized Message Authentication Code Generation Function (OMGF) tomaintain security without compromising energy and processing power consumption. The proposed security algorithms reduce the computational requirements for sub key generation and MAC generation in low power devices. The experimental results are compared with the existing security algorithms like RC5 and SHA, and is proven that R2CV and OMGF reduce the time consumed, increase battery life and in turn it extends the network life time.
    Keywords: IoT Security; low-power devices; Message authentication code; Energy efficiency; Internet of Things.

  • Real-Time Physical Register File Allocation with Neural Networks for Simultaneous Multi-Threading Processors   Order a copy of this article
    by Wenjun Wang, Wei-Ming Lin 
    Abstract: Simultaneous Multi-Threading (SMT) processors improve system performance by allowing concurrent execution of multiple independent threads with shared key resources. Physical register file, shared among the threads in real time, is one of the most critical resources in deciding overall system performance. Disproportional distribution of registers among the threads may easily hamper normal processing of some threads. In this paper, we develop a machine learning algorithm to efficiently allocate registers among concurrent executing threads based on current resource utilization circumstances. An off-line training process is first employed to establish a well-trained neural network which is then applied to dynamically adjust the resource distribution in real time. Our experiment results on M-sim, which is a multi- threaded micro-architectural simulation environment, show that our proposed technique significantly improves the average system throughput by up to 42% without sacrificing execution fairness among the threads.
    Keywords: Simultaneous Multi-Threading; Register Re- naming; Physical Register File; Neural Networks; Machine Learning.

  • Multiprocessing Scalable String Matching Algorithm for Network Intrusion Detection System   Order a copy of this article
    by Adnan Hnaif, Ali Aldahoud, Mohammad Alia, Issa Al’otoum, Duaa Hani 
    Abstract: With high increasing speed of today's computer networks which affects the performance of security issues in terms of detection speed, the traditional security tools such as firewall is insufficient to protect the networks from external threads. Intrusion Detection Systems (IDS) are one of the most reliable tools that can be used to monitor all the network traffic to identify unauthorized usage of computer system networks.rnIn this paper, we have proposed a scalable string matching algorithm based on Network IDS (NIDS) to enhance the speed of NIDS detection engine, which called Multiprocessing Scalable String Matching Algorithm for Network Intrusion Detection System (MSNIDS). The MSNIDS implemented by using enhanced weighted exact matching algorithm (EWEMA) in both sequential and parallel processing. The MSNIDS based on EWEMA can be achieved more than 89% in sequential processing time compared with WEMA, and 86% in parallel processing time compared with sequential matching processing.
    Keywords: String Matching Algorithms; Distributed Architecture; Parallel Processing; Network Intrusion Detection System.

Special Issue on: On-Chip Communication Theory and Applications

  • Parallel Video Processing on FPGA Architecture   Order a copy of this article
    by Lamjed Touil, Abdessalem Bn Abdelali, Lilia Kechiche, Bouraoui Ouni, Abdelatif MTIBAA 
    Abstract: Real time Video applications are becoming widely used in many domains with more demand for high performance. Video processing is intensive and habitually has accompanying real-time or super-real-time requirements. Such us, Multiple cameras are used in monitoring and surveillance systems in automatically real time analyze video to detect unusual events. Due to the strong computational imposed by video algorithms, real-time video treatment is notably amenable to concurrent processing. Classical implementation solutions whether based on general purpose processors or dedicated ones like DSP cannot fulfill wanted performance. In this article, we focus on the applicability of computing reconfigurable architectures to parallel video processing applications. The experiment results show that the proposed hardware-oriented multi-treatment architecture can provide an average frame rate of 45 frames/s at high definition resolution. Statistics show a consumption about 18 % of logic resources and 27% of on chip memory which gives the possibility to integrate additional treatments.
    Keywords: FPGA; MPMC; Video processing; Cut Detection; Picture in Picture.