Title: A new method of fault tolerance based on partial reconfiguration

Authors: Long Bangqiang; Zeng Zhoumo; Dai Jing

Addresses: State Key Laboratory of Precision Measuring Technology and Instruments, Tianjin University, Tianjin 300072, China; School of Electronics and Information Engineering, Tianjin Polytechnic University, Tianjin 300384, China ' State Key Laboratory of Precision Measuring Technology and Instruments, Tianjin University, Tianjin 300072, China; School of Electronics and Information Engineering, Tianjin Polytechnic University, Tianjin 300384, China ' School of Electronics and Information Engineering, Tianjin Polytechnic University, Tianjin 300384, China

Abstract: When field programmable gate array (FPGA) applied in the space, it is easily subjected to the single event upset (SEU) effect which will cause the system breaking down. This paper introduces the principle of dynamic reconfiguration of FPGA, and puts forward a new design method based on embedded system with traditional fault-tolerant methods being analysed. It combines the triple modular redundancy (TMR) technique and the FPGA dynamic partial reconfiguration technique, to make the system complete self-detecting and self-healing. The design has been validated and analysed through simulation and testing, and the results turns to indicate that the new design method has strong ability of fault tolerance as well as highly credibility compared with traditional TMR technique.

Keywords: triple modular redundancy; TMR; single event upset; SEU; fault tolerance; partial reconfiguration; field programmable gate arrays; FPGA; embedded systems; system self-healing; simulation.

DOI: 10.1504/IJICT.2016.078882

International Journal of Information and Communication Technology, 2016 Vol.9 No.2, pp.232 - 241

Received: 12 Jul 2014
Accepted: 12 Sep 2014
Published online: 04 Sep 2016 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article