A new method of fault tolerance based on partial reconfiguration
by Long Bangqiang; Zeng Zhoumo; Dai Jing
International Journal of Information and Communication Technology (IJICT), Vol. 9, No. 2, 2016

Abstract: When field programmable gate array (FPGA) applied in the space, it is easily subjected to the single event upset (SEU) effect which will cause the system breaking down. This paper introduces the principle of dynamic reconfiguration of FPGA, and puts forward a new design method based on embedded system with traditional fault-tolerant methods being analysed. It combines the triple modular redundancy (TMR) technique and the FPGA dynamic partial reconfiguration technique, to make the system complete self-detecting and self-healing. The design has been validated and analysed through simulation and testing, and the results turns to indicate that the new design method has strong ability of fault tolerance as well as highly credibility compared with traditional TMR technique.

Online publication date: Sun, 04-Sep-2016

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