Int. J. of Wireless and Mobile Computing   »   2015 Vol.9, No.4

 

 

Title: Design and comparison of 0.18-µm CMOS power amplifiers for ultra-wide-band applications

 

Authors: Vishakha P. Bhale; Upena D. Dalal; Rajendra M. Patrikar

 

Addresses:
Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology (SV NIT), Surat, Gujarat, India
Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology (SV NIT), Surat, Gujarat, India
Department of Electronics Engineering, Visvesvaraya National Institute of Technology (V NIT), Nagpur, Maharashtra, India

 

Abstract: With the help of standard power amplifier design steps, four class AB power amplifier topologies are designed and compared using 0.18-μm CMOS process for 3-5-GHz ultra-wide-band applications. The proposed four topologies are: basic common source topology, cascode topology, cascoded current reused topology, and the two-stage power amplifier topology. Comparison of the four designs has been made to the parameters such as power gain, input and output matching, reverse isolation, power-added efficiency, stability, and linearity and noise figure. By comparison, it is found that the two-stage design with cascoded current reused topology as first stage and common source topology as second stage achieves the best performance among the four designs.

 

Keywords: cascode topology; current reused topology; efficiency; group delay; CMOS power amplifiers; resistive feedback; source degeneration; shunt peaking; stability; UWB applications; ultra-wideband; linearity; power amplifier design; common source topology.

 

DOI: 10.1504/IJWMC.2015.074038

 

Int. J. of Wireless and Mobile Computing, 2015 Vol.9, No.4, pp.307 - 316

 

Submission date: 31 Jan 2015
Date of acceptance: 10 Jul 2015
Available online: 02 Jan 2016

 

 

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