Title: Reconfigurable wrapper architecture for UART CORE testing using FSM approach

Authors: K. Chakrapani; P. Neelamegam

Addresses: Department of Information Technology, SASTRA University, Thirumalaisamudhram, Thanjavur, Tamil Nadu, India ' School of Electrical and Electronics Engineering, SASTRA University, Thirumalaisamudhram, Thanjavur, Tamil Nadu, India

Abstract: The UART is a device used for communication of data either in asynchronous or synchronous mode. Nowadays, more number of designers introduces UART as a system on chip for various purposes. These UART SoC cores are to be checked on the basis of its compatibility and performance and a complete study is advisable. For this purpose, a reusable and reconfigurable wrapper architecture is designed, which is based on a finite machine called the wrapper finite state machine (WFSM) in Verilog and its baud rate as well as frame bit rate is computed. This WFSM monitors and verifies bit rate, packet transmission with single stop bit and two stop bits, with and without parity bits, distance coverage, frame transmission time, junk handling, utilisation of CUP, utilisation of power by UART with wrapper in FPGA are studied at different baud rates. It is designed and implemented in Quarters II in CyclonII (DEI) FPGA with the help of Zero-Plus logic analyzer.

Keywords: universal asynchronous receiver/transmitter; UART; SoC; system-on-a-chip; reusable wrapper; FPGA; reconfigurable wrapper architecture; wrapper FSM; finite state machines; WFSM; field-programmable gate arrays.

DOI: 10.1504/IJAIP.2015.073713

International Journal of Advanced Intelligence Paradigms, 2015 Vol.7 No.3/4, pp.326 - 341

Received: 01 Nov 2014
Accepted: 01 May 2015
Published online: 16 Dec 2015 *

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