Reconfigurable wrapper architecture for UART CORE testing using FSM approach Online publication date: Wed, 16-Dec-2015
by K. Chakrapani; P. Neelamegam
International Journal of Advanced Intelligence Paradigms (IJAIP), Vol. 7, No. 3/4, 2015
Abstract: The UART is a device used for communication of data either in asynchronous or synchronous mode. Nowadays, more number of designers introduces UART as a system on chip for various purposes. These UART SoC cores are to be checked on the basis of its compatibility and performance and a complete study is advisable. For this purpose, a reusable and reconfigurable wrapper architecture is designed, which is based on a finite machine called the wrapper finite state machine (WFSM) in Verilog and its baud rate as well as frame bit rate is computed. This WFSM monitors and verifies bit rate, packet transmission with single stop bit and two stop bits, with and without parity bits, distance coverage, frame transmission time, junk handling, utilisation of CUP, utilisation of power by UART with wrapper in FPGA are studied at different baud rates. It is designed and implemented in Quarters II in CyclonII (DEI) FPGA with the help of Zero-Plus logic analyzer.
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