A 24.5 mW, 10-bit, 50 MS/sec CMOS pipelined analogue-to-digital converter Online publication date: Mon, 13-Feb-2012
by D. Meganathan
International Journal of High Performance Systems Architecture (IJHPSA), Vol. 3, No. 4, 2011
Abstract: This paper presents the design of a low-power, medium-resolution, high-speed pipelined analogue-to-digital converter (ADC). A low-power front-end track-and-hold amplifier (THA) is realised to reduce sampling time uncertainty error. The paper also includes the design of low-power, high-bandwidth, high-gain operational transconductance amplifiers (OTAs). The OTAs are used in ADC to reduce finite OTA gain and OTA settling time non-linearity errors. Low power circuit techniques are employed to minimise overall power consumption of the ADC. The proposed ADC is implemented in 180 nm digital CMOS technology. The converter achieves signal-to-noise distortion ratio of 59.8 dB/57.9 dB, spurious-free dynamic range of 89 dB/86.6 dB and effective number of bits of 9.64-bits/9.33-bits at sampling speed of 50 MHz with the input signal frequencies of 4 MHz/Nyquist frequency. The peak differential-non-linearity of the converter is 0.28/-0.17 LSB and integral-non-linearity of the converter is +0.42/-0.41 LSB. The proposed 10-bit, 50 MS/sec pipelined ADC consumes 24.5 mW amount of power from 1.8 V supply.
Online publication date: Mon, 13-Feb-2012
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