A HW/SW design methodology for embedded SIMD vector signal processors Online publication date: Sun, 14-Sep-2008
by J.P. Robelly, G. Cichon, H. Ahlendorf, G. Fettweis
International Journal of Embedded Systems (IJES), Vol. 3, No. 3, 2008
Abstract: The trend of using SIMD processors in embedded systems has been driven by signal processing applications with large computational requirements. In this paper, we report a HW/SW methodology in order to design DSP cores and algorithms that exploit SIMD parallelism. Starting point is a novel hardware architectural template called STA. We introduce an approach for automatic generation of simulation and hardware models of DSP cores with a scalable level of SIMD parallelism. Software development is based on an algebraic model that captures the SIMD computational model. We explain how algorithms can be designed independent of the available SIMD parallelism.
Online publication date: Sun, 14-Sep-2008
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