Divide-by-16/17 dual modulus prescaler design with enhanced speed in a 180nm CMOS technology Online publication date: Mon, 26-Apr-2021
by Uma Nirmal; V.K. Jain
International Journal of Computer Aided Engineering and Technology (IJCAET), Vol. 14, No. 3, 2021
Abstract: In this work, we propose a high-speed dual modulus divide by 16/17 prescaler Design IV with 8.9 GHz operating rate. It uses RE-3 type DFF in synchronous divide by 2/3 prescaler design and asynchronous divide by 8 counter design. It reduces: design complexity, capacitive loading and delay. The proposed Design IV shows better results in terms of both speed and power performance than other ratioed and ratioless divide by 16/17 prescalers. It is implemented in a 180 nm CMOS technology and consumes only 0.38 mW power from a 1V supply voltage. The speed of the new Design IV is improved by ~53% compared with conventional circuits with operating frequency 5.8 GHz.
Online publication date: Mon, 26-Apr-2021
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