A robust error control coding-based watermarking algorithm for FPGA IP protection Online publication date: Wed, 05-Aug-2020
by Zhenyu Liu; Xin Su; Dafang Zhang; Jing Long
International Journal of Embedded Systems (IJES), Vol. 13, No. 2, 2020
Abstract: The ownership of intellectual property (IP) for integrated circuit (IC) is difficult to identify when the watermarks are attacked and damaged in previous work. To address this issue, we propose a robust error control coding (ECC)-based watermarking algorithm for FPGA IP protection. Firstly, the Blakley threshold scheme is used to share the signature of IP user and generate watermarks. The watermarks are then encrypted and finally embedded into FPGA IP design. The signature sharing makes it unnecessary to ensure that all watermarks are reliable in authentication. The complete signature can be retrieved with several watermarks even if other watermarks are damaged. Secondly, the IP owner's image signature is used for copyright identification, and the image is shared by the threshold multi-secret sharing method to solve the resource overhead problem. The image itself is fault-tolerant. Even if the image has a bit error rate of 16.74%, the copyright content can be successfully identified. The fault tolerance of the image has greatly improved the robustness of the watermark. Experiments show that the algorithm not only has low overhead for watermark embedding, but also achieves good results in terms of robustness.
Online publication date: Wed, 05-Aug-2020
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