Authors: Alexandre Solon Nery; Alexandre Da Costa Sena; Leandro S. Guedes
Addresses: Departamento de Engenharia Elétrica, Universidade de Brasília, Brasília, DF, Brazil ' Departamento de Informática e Ciência da Computação, Universidade do Estado do Rio de Janeiro, Rio de Janeiro, RJ, Brazil ' Departamento de Informática, Instituto Federal de Educação, Ciência e Tecnologia de Mato Grosso do Sul, Corumbá, MS, Brazil
Abstract: Pathfinding algorithms are at the heart of several classes of applications, such as network appliances (routing) and autonomous vehicle navigation. Thus, this work aims at designing and evaluating an efficient pathfinding FPGA accelerator based on Dijkstra's shortest path algorithm to mitigate the increasing network traffic problem at the edge of the network. The system is designed using Xilinx High-Level Synthesis (HLS) compiler and is implemented in the programming logic of a Xilinx Zynq FPGA, embedded with an ARM microprocessor which is not only in charge of controlling the co-processor but also in charge of lightweight TCP/IP network communication. Extensive performance, circuit-area, and energy consumption results show that the co-processor can find the shortest path about 2.5 times faster than the system's ARM microprocessor, on a simulation scenario test case based on touristic locations in the city of Rio de Janeiro, acquired from the OpenStreetMap database.
Keywords: pathfinding; FPGA accelerator; high-level synthesis; fog computing; edge computing.
International Journal of Grid and Utility Computing, 2019 Vol.10 No.3, pp.212 - 223
Available online: 15 May 2019 *Full-text access for editors Access for subscribers Purchase this article Comment on this article