Title: Symmetric encryption in reconfigurable and custom hardware

Authors: Eric J. Swankoski, N. Vijaykrishnan, R. Brooks, M. Kandemir, M.J. Irwin

Addresses: US Naval Research Laboratory, Washington, DC 20375, USA. ' Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16802, USA. ' Holcombe Department of Electrical and Computer Engineering, Clemson University, 313-C Riggs Hall, PO Box 340915, Clemson, SC 29634-0915, USA. ' Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16802, USA. ' Department of Computer Science and Engineering, Pennsylvania State University, University Park, PA 16802, USA

Abstract: Software implementations of many symmetric-key encryption algorithms are often inefficient. We study the AES algorithm and its optimised implementations in both software and hardware. Specifically, the performance of AES encryption in processor architectures is considered. Also, we study the performance of optimised AES implementations in Xilinx FPGAs and ASIC devices. We illustrate how modern processors are inadequate when implementing the AES algorithm in terms of performance and power consumption. By comparison, implementations of the AES encryption architectures in FPGAs demonstrate a performance improvement ranging from 50% to approximately 2000%. ASIC implementations are able to achieve even higher performance.

Keywords: FPGA; ASIC; encryption; AES algorithm; symmetric key; security; processors; software; custom hardware; reconfigurable architectures; cryptography.

DOI: 10.1504/IJES.2005.009950

International Journal of Embedded Systems, 2005 Vol.1 No.3/4, pp.205 - 217

Published online: 05 Jun 2006 *

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