Title: Electro-thermal assessment of heterojunction tunnel-FET for low-power digital circuits

Authors: T.P. Dash; Sanghamitra Das; S. Dey; C.K. Maiti

Addresses: Department of Electronics and Communication Engineering, Siksha 'O' Anusandhan (Deemed to be University), Bhubaneswar, Odisha 751030, India ' Department of Electronics and Communication Engineering, Siksha 'O' Anusandhan (Deemed to be University), Bhubaneswar, Odisha 751030, India ' Department of Electronics and Communication Engineering, Siksha 'O' Anusandhan (Deemed to be University), Bhubaneswar, Odisha 751030, India ' Department of Electronics and Communication Engineering, Siksha 'O' Anusandhan (Deemed to be University), Bhubaneswar, Odisha 751030, India

Abstract: To overcome the fundamental limitations of conventional MOSFETs, tunnel field effect transistors (TFETs) with strained-SiGe channel (via heterogeneous integration) may be used and is demonstrated using TCAD simulations. We mainly focus on the design and implementation of silicon-germanium (SiGe)-based tunnel field effect transistor, aiming to reduce the device operation voltage down to below 0.5 V. Physics-based electro-thermal simulations are performed for evaluating the self-heating (temperature rise) in the devices. We present the results of the electro-thermal analysis supported by effective 2D and 3D device simulations. Performance improvement in drain current as high as 200% has been achieved.

Keywords: heterostructure tunnel FET; strained-SiGe; heterogeneous integration; electro-thermal simulation.

DOI: 10.1504/IJNP.2019.099185

International Journal of Nanoparticles, 2019 Vol.11 No.2, pp.154 - 166

Received: 06 Dec 2017
Accepted: 26 Oct 2018
Published online: 19 Apr 2019 *

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