Title: Impact of structural parameters on DC performance of recessed channel SOI-MOSFET

Authors: Sikha Mishra; Urmila Bhanja; G.P. Mishra

Addresses: Department of Electronics and Communication Engineering, Institute of Technical Education and Research, Device Simulation Lab, Siksha 'O' Anusandhan (Deemed to be University), Khandagiri, Bhubaneswar, 751030, India ' Department of Electronics and TC Engineering, IGIT, Saranga, Dhenkanal, India ' Department of Electronics and Communication Engineering, Institute of Technical Education and Research, Device Simulation Lab, Siksha 'O' Anusandhan (Deemed to be University), Khandagiri, Bhubaneswar, 751030, India

Abstract: With the concept of groove gate and implementing the idea of silicon on insulator (SOI), a new analytical model is developed for the rectangular recessed channel silicon on insulator (RRC-SOI) metal oxide semiconductor field effect transistor (MOSFET). This analytical model is formulated using 2D Poisson's equation and develops a compact equation for threshold voltage using minimum surface potential. This paper analyses the effect of negative junction depth (NJD) on device parameters, such as minimum surface potential, threshold voltage, sub-threshold slope (SS), and drain induced barrier lowering (DIBL). The impact of oxide thickness variation on the above parameters has also been evaluated. Further, the linearity performance in terms of figure of merits (FOM) and device parameters like drain current and trans-conductance of the proposed model is compared with the simulated results of rectangular recessed channel (RRC) MOSFET. The validity of the proposed model has been verified with simulation results performed on Sentaurus TCAD device simulator.

Keywords: short-channel effects; SCEs; silicon on insulator; SOI; rectangular recessed channel; RRC; negative junction depth; NJD.

DOI: 10.1504/IJNP.2019.099184

International Journal of Nanoparticles, 2019 Vol.11 No.2, pp.140 - 153

Available online: 29 Mar 2019 *

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