Title: Reduced ordered binary decision diagram-based combinational circuit synthesis for optimising area, power and temperature
Authors: Apangshu Das; Akash Debnath; Sambhu Nath Pradhan
Addresses: Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Tripura, 799046, India ' Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Tripura, 799046, India ' Department of Electronics and Communication Engineering, National Institute of Technology Agartala, Tripura, 799046, India
Abstract: In this paper, an attempt is made to reduce the rise in circuit temperature by optimising power-density during logic synthesis level. Reduced ordered binary decision diagram (ROBDD) being canonical in nature makes a suitable choice of logic realisation in this work. ROBDD is used here not only to reduce area (node) but also the possibility of reducing power and temperature (power-density) is explored. In this work, a genetic algorithm based approach is presented to determine a suitable variable ordering during the formation of the ROBDD for its thermal-aware realisation considering other parameters like area and power without performance degradation. The proposed approach shows more than 33% savings in area and power, and 5.61% savings in power-density with respect to initial ROBDD representation of LGSynth93 benchmark circuits. Actual on-chip area, power dissipation and the absolute value of temperature are calculated using CADENCE and HotSpot tool to validate the power-density based results.
Keywords: binary decision diagram; BDD; reduced ordered binary decision diagram; ROBDD; area power power-density trade-offs; genetic algorithm; variable ordering; temperature; HotSpot.
International Journal of Nanoparticles, 2019 Vol.11 No.2, pp.94 - 112
Available online: 29 Mar 2019 *Full-text access for editors Access for subscribers Purchase this article Comment on this article