Title: Design of 5-3 multicolumn compressor for high performance multiplier

Authors: R. Marimuthu; S. Balamurugan; P.S. Mallick

Addresses: School of Electrical Engineering, VIT University, Vellore – 632014, Tamilnadu, India ' School of Electrical Engineering, VIT University, Vellore – 632014, Tamilnadu, India ' School of Electrical Engineering, VIT University, Vellore – 632014, Tamilnadu, India

Abstract: Compressors are widely used in multiplier to reduce the partial products. This paper proposed the design of 5-3 multicolumn compressor. The proposed 5-3 multicolumn compressor is used to design the various size multipliers. In this paper, we have designed 6 × 6, 8 × 8, 10 × 10 and 12 × 12 bit multiplier using proposed 5-3 multicolumn compressor, conventional 5-3 multicolumn compressor and conventional 4-2 compressor and compared the results. Simulation result shows that the proposed architecture consumes less power and provides more speed than conventional multicolumn 5-3 compressor and conventional 4-2 compressor. Cadence RTL compiler is used to obtain the results of multiplier.

Keywords: full adder; 5-3 multicolumn compressor; multiplier; energy delay product; EDP.

DOI: 10.1504/IJCAET.2018.094334

International Journal of Computer Aided Engineering and Technology, 2018 Vol.10 No.5, pp.568 - 575

Received: 09 Apr 2016
Accepted: 27 Aug 2016

Published online: 11 Jun 2018 *

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