Title: HtComp: bringing reconfigurable hardware to future high-performance applications

Authors: Alessandro Cilardo

Addresses: University of Naples Federico II, Centro Regionale Information and Communication Technology (CeRICT), Naples, Italy

Abstract: Current trends in computer architecture are increasingly moving towards heterogeneous platforms, now including FPGAs as first-class components enabling unprecedented levels of performance and power-efficiency. Programming such next-generation machines is however extremely difficult as it requires architecture-specific code and low-level hardware design. This paper describes the main outcomes of the HtComp project, a two-year research programme aimed at exploring methodologies and tools allowing the automated generation of FPGA-based accelerators from high-level applications written in traditional software languages. In particular, the paper describes the main contributions brought by the project, covering the generation of hardware systems from high-level parallel code, the performance-oriented optimisation of memory architectures tailored on the application access patterns, as well as the automated definition of application-driven special-purpose on-chip interconnects. Overall, the above innovations contributed to creating a viable path allowing generic software developers to access tomorrow's hardware-accelerated high-performance platforms with minimum development overheads.

Keywords: FPGAs; HPC; reconfigurable computing; GPU-like computing; memory partitioning; on-chip interconnect synthesis.

DOI: 10.1504/IJHPCN.2018.093843

International Journal of High Performance Computing and Networking, 2018 Vol.12 No.1, pp.74 - 83

Received: 03 Feb 2016
Accepted: 07 Jul 2016

Published online: 27 Jul 2018 *

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