Title: Low power low voltage CMOS full adder cells based on energy-efficient architecture

Authors: Pankaj Kumar; Rajender Kumar Sharma

Addresses: Department of Electronics & Communication Engineering, National Institute of Technology, Kurukshetra, Haryana, India ' Department of Electronics & Communication Engineering, National Institute of Technology, Kurukshetra, Haryana, India

Abstract: This paper presents two low power full adder cells based on energy-efficient internal logic approach and pass transistor logic. These two new designs successfully operate at low voltage with tremendous signal integrity and driving capability. These designs are tested on a common environment using 90-nm CMOS process technology at many supply voltages. The adder cells are compared with eight of the popularly known full adders based on power consumption, speed and power-delay-product (PDP) and area efficiency. Intensive simulation runs on cadence environment and spectra shows that proposed full adder cells outperform their counterparts exhibiting 59.48% and 55.41% improvement in their PDP metrics.

Keywords: low power; high speed; low voltage; hybrid design; energy efficient; full adder.

DOI: 10.1504/IJCAT.2018.093530

International Journal of Computer Applications in Technology, 2018 Vol.57 No.4, pp.291 - 301

Received: 19 Oct 2016
Accepted: 02 May 2017

Published online: 13 Jul 2018 *

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