Title: Implementation of quadruple valued flip-flops using CMOS and spatial light modulator-based Savart plate

Authors: Animesh Bhattacharya; Amal K. Ghosh; Goutam K. Maity

Addresses: Department of Applied Electronics and Instrumentation Engineering, Netaji Subhash Engineering College, Garia, Kolkata-152, India ' Department of Applied Electronics and Instrumentation Engineering, Netaji Subhash Engineering College, Garia, Kolkata-152, India ' Department of Physics, Pingla Thana Mahavidyalaya, Maligram, Paschim Medinipur – 721140, West Bengal, India

Abstract: The designing and simulation of multi-valued logic (MVL) is a very interesting and important task in the present scenario. The memory devices in MVL system are the most important area of modern research. The MVL system consists of a number of intermediate states between the true and false instead of the conventional binary logic consists of only two states - 'true' and 'false'. Hence, the MVL enables more information to be handled in a much compact manner, especially suitable for handling big data. In quadruple valued logic (QVL) system, the additional two intermediate states are denoted as 'partially known' and 'partially unknown' which can be explored significantly to sequential logics also, e.g., flip-flops, etc. The present paper deals with the design and simulation of different kind of flip-flops in QVL system, using complementary metal oxide semiconductor (CMOS) and its optical implementation using spatial light modulator (SLM) and Savart plate.

Keywords: complementary metal oxide semiconductor; CMOS; flip-flop; multi-valued logic; MVL; NAND gate; quadruple valued logic; QVL; Savart plate; spatial light modulator; SLM; Tanner EDA tools.

DOI: 10.1504/IJNP.2018.092684

International Journal of Nanoparticles, 2018 Vol.10 No.1/2, pp.141 - 164

Received: 20 Dec 2017
Accepted: 20 Jan 2018

Published online: 19 Jun 2018 *

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