Title: Macro-models for high-level area and power estimation on FPGAs

Authors: Tianyi Jiang, Xiaoyong Tang, Prith Banerjee

Addresses: Electrical and Computer Engineering Northwestern University, 2145 Sheridan Road, Evanston, IL 60208, USA. ' Electrical and Computer Engineering Northwestern University, 2145 Sheridan Road, Evanston, IL 60208, USA. ' Electrical and Computer Engineering Northwestern University, 2145 Sheridan Road, Evanston, IL 60208, USA

Abstract: This paper presents the high-level equation based area and power macro-models for various RTL level operators on FPGAs. The area model is parameterised with the bit width of the device and the power model takes into account input switching activity and input spatial correlation as well as input bit width. These models are derived by actual synthesis of these RTL operators using back-end logic synthesis and place-and-route tools. Compared with the other approaches, our method generated a uniform macro-model for each operator with fewer coefficients and sometimes lower degrees. It is also easier to analyse the power sensitivity to different parameters.

Keywords: macro-models; high-level synthesis; area estimation; power estimation; FPGAs; modelling; RTL operators; field programmable gate arrays; register transfer level.

DOI: 10.1504/IJSPM.2006.009007

International Journal of Simulation and Process Modelling, 2006 Vol.2 No.1/2, pp.12 - 19

Published online: 12 Feb 2006 *

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