Title: Efficient hardware architecture for integer implementation of multi-alphabet arithmetic coding for data mining
Authors: S.D. Jayavathi; A. Shenbagavalli; B. Ganapathy Ram
Addresses: Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, Tamil Nadu, India ' Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, Tamil Nadu, India ' Department of Electronics and Communication Engineering, National Engineering College, Kovilpatti, Tamil Nadu, India
Abstract: The aim of this paper is to create an efficient hardware architecture for the multi-alphabet arithmetic coding (MA-AC) in semicustom and full custom application specific integrated circuit (ASIC). Generally, hardware realisation of MA-AC involves numerical processing and entropy coding, which employ the floating point (FP) arithmetic which is replaced by integer implementation in such a way that the symbol counts are used instead of probabilities. Novel hardware architecture is designed by modifying the update equations for upper and lower limits of multi-alphabet arithmetic encoder and decoder based on the update equation of the FP implementation. The proposed hardware architectures are synthesised in Xilinx and Altera Field Programmable Gate Array (FPGA) devices to evaluate resource utilisation and speed. Also, the physical design is encountered as ASIC device using Cadence Design environment tsmc 0.18 µm technology which shows area reduction of 12.75% and 23.61% and power consumption of 29.86% and 38.89% for encoder and decoder, respectively.
Keywords: multi-alphabet arithmetic coder; encoder; decoder; state diagram; field programmable gate array; FPGA; application specific integrated circuit; ASIC.
International Journal of Business Intelligence and Data Mining, 2018 Vol.13 No.1/2/3, pp.188 - 208
Available online: 03 Nov 2017 *Full-text access for editors Access for subscribers Free access Comment on this article