Title: Optimising the performance of three-phase neutral-point clamped rectifier under disturbed AC mains

Authors: Deepak Sharma; Abdul Hamid Bhat; Aijaz Ahmad

Addresses: Department of Electrical Engineering, National Institute of Technology Srinagar, Kashmir, India ' Department of Electrical Engineering, National Institute of Technology Srinagar, Kashmir, India ' Department of Electrical Engineering, National Institute of Technology Srinagar, Kashmir, India

Abstract: In this paper, a novel simplified control technique is proposed to control three-phase neutral-point clamped bidirectional rectifier using optimised switching sequences for disturbed AC mains. In space-vector modulation (SVM) technique using optimised switching sequences, duty ratio and sampling periods in each region are very important. In other words, reference vector trajectory shape and the time spent by the reference vector in each region are very important to obtain exact switching under any supply conditions. With the use of optimised switching sequences, even under ideal supply conditions, it is depicted that source-side and load-side parameters deviate from acceptable limits, and a DC-bus capacitor voltage unbalance occurs. Under the influence of disturbed AC supply, source-side and load-side parameters deviate more beyond acceptable limits which cause a very large unbalance in DC bus capacitor voltages. This non-ideal performance of the converter is responsible for the deterioration of quality of source currents and a large stress on power semiconductor devices. A new algorithm is proposed in this paper to make the converter performance ideal even under ideal and non-ideal supply conditions. According to supply conditions, the proposed technique varies the speed of the reference vector and, also at the same time, forms a required trajectory while passing through the most effective regions of SVM hexagon. The proposed technique maintains parameters within acceptable limits for source side and load side in terms of unity power factor, low input current total harmonic distortion (THD), minimum switching losses and reduced-rippled, well-regulated DC-bus voltage and also at the same time DC-bus capacitor voltage balance. The simulation results are presented to demonstrate the effectiveness of the proposed control technique.

Keywords: DC-bus capacitor voltage unbalancing; disturbed AC mains; harmonics compensation; multilevel converters; neutral-point clamped converter; NPC converter; power quality; space-vector pulse width modulation; SVPWM.

DOI: 10.1504/IJPELEC.2018.088379

International Journal of Power Electronics, 2018 Vol.9 No.1, pp.99 - 121

Received: 02 Jan 2017
Accepted: 08 May 2017
Published online: 05 Dec 2017 *

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