Authors: Baisakhi Das; Biplab K. Sikdar
Addresses: Department of Information Technology, Guru Nanak Institute of Technology, Kolkata, India ' Department of Computer Science and Technology, Indian Institute of Engineering and Science and Technology, Shibpur, India
Abstract: In CMPs (Chip Multi-Processors), with thousand of processors, the issue of power dissipation has emerged as a matter of serious concern. Out of several factors responsible for huge power drainage the branch prediction unit of a processor contributes almost 10% of the overall power dissipation. This work aims to analyse the impact of inaccurate/faulty design on the branch predictors' power dissipation while realising speculative execution. The issue has been addressed through introduction of probable faults in a predictor that lead to mis-speculation. The prediction mechanism in CMPs also plays a role in dead-block identification, that is to avoid unutilised power consumption in a system as well as to overcome the poor cache efficiency. The performance loss of a system due to design inaccuracies/faults in dead-block prediction is also evaluated. The detail analysis reveals that the design inaccuracies of a predictor can cause a huge power loss, even up to 95%. The additional power loss in a processor can effectively be sensed to enable diagnosis of the faulty module (design inaccuracies) of predictor as well as to frame guidelines for operating mode of a CMP's cache system.
Keywords: CMPs; branch predictor; dead block prediction; speculative execution.
International Journal of Computer Applications in Technology, 2017 Vol.56 No.3, pp.198 - 209
Received: 25 May 2016
Accepted: 07 Dec 2016
Published online: 29 Nov 2017 *