Title: Realisation of optimised eight-bit binary shifter using reversible logic approach

Authors: Vandana Shukla; O.P. Singh; G.R. Mishra; R.K. Tiwari

Addresses: Amity School of Engineering and Technology, Amity University Uttar Pradesh, Lucknow Campus, India ' Amity School of Engineering and Technology, Amity University Uttar Pradesh, Lucknow Campus, India ' Amity School of Engineering and Technology, Amity University Uttar Pradesh, Lucknow Campus, India ' Department of Physics and Electronics, Dr. R.M.L. Avadh University, Faizabad, India

Abstract: Among various arithmetic logic unit (ALU) and storage unit circuits of any digital computing device, shifter circuits are considered as one of the key component. Redesigning of these shifter circuits using reversible logic approach leads to the generation of low power loss digital devices. Reversible logic approach works on the concept of removing heat generating entities from the digital designs. Nanotechnology, optical computing, low power CMOS design, quantum computing etc. are some of the major areas of application for reversible design approach. Here in this paper, we propose two design approaches for the reversible realisation of eight bit binary shifter circuit with improved performance parameters as compared to the existing designs. Comparison of designs are performed on some selected parameters such as total number of reversible logic gates used in the design and total garbage outputs generated. The proposed optimised design is simulated using ModelSim software and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.

Keywords: eight bit binary shifter; reversible logic gates; low loss digital design; reversible circuit design.

DOI: 10.1504/IJSTM.2017.088156

International Journal of Services Technology and Management, 2017 Vol.23 No.4, pp.262 - 274

Received: 22 Jan 2016
Accepted: 03 Mar 2016

Published online: 21 Nov 2017 *

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