Title: Design and FPGA implementation of chaotic interleaver for IDMA system

Authors: Brahim Boukholda

Addresses: SysCom Laboratory, ENIT, University EL Manar, Tunis 1002, Tunisia

Abstract: Interleaver plays a very important role in a digital communication system. It is often used to improve the performance of forward error correcting codes. On the other side, interleaver can be used in a multiusers transmission especially in the Interleave Division Multiple Access (IDMA) technique. Indeed, in IDMA systems users are distinguished only by interleavers. Each user is identified by a specific interleaver. We will propose a method to generate chaotic interleaver based on the generation of sequences having a chaotic behaviour using some chaotic maps such as logistic function and Henon map function. In this paper, we will study the performance of chaotic interleavers with correlation analysis for IDMA system. A comparison between the proposed interleavers and other interleavers in terms of FPGA (Field Programmable Gate Array) resources and maximum operating frequency is presented. Simulations result shows that the chaotic interleaver designed is simple to generate and outperforms other interleavers to require fewest devices and best timing behaviour.

Keywords: IDMA; multiuser detection; chaotic maps; random interleavers; correlation; memory requirements; FPGA.

DOI: 10.1504/IJWMC.2017.087327

International Journal of Wireless and Mobile Computing, 2017 Vol.13 No.1, pp.1 - 7

Received: 15 Mar 2016
Accepted: 20 Oct 2016

Published online: 03 Oct 2017 *

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