Authors: Neeraj Kumar Misra; Bibhash Sen; Subodh Wairya
Addresses: Department of Electronics Engineering, Institute of Engineering and Technology, Lucknow, India ' Department of Computer Science and Engineering, National Institute of Technology, Durgapur, India ' Department of Electronics Engineering, Institute of Engineering and Technology, Lucknow, India
Abstract: Quantum-dot cellular automata are a prominent part of the nanoscale regime. They use a quantum cellular based architecture which enables rapid information process with high device density. This paper targets the two kinds of novel error control circuits such as Hamming code, parity generator and checker. To design the HG-PP (HG = Hamming gate, PP = parity preserving), NG-PP (NG = new gate) are proposed for optimising the circuits. Based on the proposed gates and a few existing gates, the Hamming code and parity generator and checker circuits are constructed. The proposed gates have been framed and verified in QCA. The simulation outcomes signify that their framed circuits are faultless. In addition to verification, physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.
Keywords: reversible computing; quantum cost; conservative gate; hamming code; parity generator and checker; quantum-dot cellular automata; error control.
International Journal of Computer Applications in Technology, 2017 Vol.56 No.1, pp.1 - 17
Received: 14 Mar 2016
Accepted: 20 Sep 2016
Published online: 12 Sep 2017 *