Authors: Wael M. El-Medany
Addresses: Computer Engineering Department, College of Information Technology, University of Bahrain, Sakhir 32038, Bahrain
Abstract: This paper presents an efficient, reconfigurable, high throughput IP core implementation of a Cyclic Redundancy Check (CRC) chip design on Field Programmable Gate Array (FPGA). The IP core design has the advantage of correcting multiple errors based on the chosen CRC generator polynomial. The design includes both of the CRC encoder and decoder systems to be used for the serial data transmission and reception of the Wireless Transceiver System. VHDL (VHSIC Hardware Description Language) has been used for describing the hardware of the encoder and decoder systems chip. The IP core design can be reconfigured with different code lengths, maximum burst lengths, and CRC types. It also provides high flexibility by processing various different burst types during runtime. We show detailed simulation and implementation results to demonstrate the performance and hardware complexity of our core. The design has been simulated and tested using ISim (VHDL/Verilog). Spartan 3AN FPGA starter kit from Xilinx has been used for downloading the design into Xilinx chip.
Keywords: FPGA; CRC code; IP core; VLSI.
International Journal of Computer Applications in Technology, 2017 Vol.55 No.4, pp.257 - 265
Available online: 04 Aug 2017 *Full-text access for editors Access for subscribers Purchase this article Comment on this article