Title: Fault masking issue on a dependable processor using BIST under highly electromagnetic environment

Authors: Aromhack Saysanasongkham; Satoshi Fukumoto; Masayuki Arai

Addresses: Graduate School of System Design, Tokyo Metropolitan University, 6-6, Asahigaoka, Hino, Tokyo 191-0065, Japan ' Faculty of System Design, Tokyo Metropolitan University, 6-6, Asahigaoka, Hino, Tokyo 191-0065, Japan ' College of Industrial Technology, Nihon University, 1-2-1 Izumicho, Narashino, Chiba 275-8575 Japan

Abstract: While power converter and inverter circuits have been enhanced for higher switching speed, higher voltage and higher power density, there are arising problems relating to the effect of near-field noise due to high-current pulse, which can severely affect the operations of the controllers for power converters and the surrounding logic circuits as multi-bit transient faults. A scheme to construct highly reliable processors which measures the noise duration by built-in self test (BIST) and avoids its effect by clock mitigation was proposed in our previous work. However, in some cases, the upper bounds of the noise duration distribution are underestimated due to insufficient testing and fault masking, resulting in faulty operations. In this paper, we further investigate these underestimating situations and then propose a test method to overcome the problem. We use SPICE simulation to evaluate the effectiveness of the proposed scheme.

Keywords: fault masking; online built-in self test; BIST; periodical multi-bit transient fault; noise avoidance; dependable processor; electromagnetic radiation.

DOI: 10.1504/IJCSE.2017.084681

International Journal of Computational Science and Engineering, 2017 Vol.14 No.4, pp.309 - 320

Received: 23 Sep 2015
Accepted: 01 Nov 2015

Published online: 21 Jun 2017 *

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