Title: pvFPGA: paravirtualising an FPGA-based hardware accelerator towards general purpose computing

Authors: Wei Wang; Miodrag Bolic; Jonathan Parri

Addresses: Computer Architecture Research Group, University of Ottawa, 800 King Edward, Ottawa, Ontario, Canada ' Computer Architecture Research Group, University of Ottawa, 800 King Edward, Ottawa, Ontario, Canada ' Computer Architecture Research Group, University of Ottawa, 800 King Edward, Ottawa, Ontario, Canada

Abstract: This paper presents an ameliorated design of pvFPGA, which is a novel system design solution for virtualising an FPGA-based hardware accelerator by a virtual machine monitor (VMM). The accelerator design on the FPGA can be used for accelerating various applications, regardless of the application computation latencies. In the implementation, we adopt the Xen VMM to build a paravirtualised environment, and a Xilinx Virtex-6 as an FPGA accelerator. The data transferred between the x86 server and the FPGA accelerator through direct memory access (DMA), and a streaming pipeline technique is adopted to improve the efficiency of data transfer. Several solutions to solve streaming pipeline hazards are discussed in this paper. In addition, we propose a technique, hyper-requesting, which enables portions of two requests bidding to different accelerator applications to be processed on the FPGA accelerator simultaneously through DMA context switches, to achieve request level parallelism. The experimental results show that hyper-requesting reduces request turnaround time by up to 80%.

Keywords: field-programmable gate array; FPGA; hardware accelerator; virtualisation; hyperrequesting; streaming pipeline; DMA context switch.

DOI: 10.1504/IJHPCN.2017.084246

International Journal of High Performance Computing and Networking, 2017 Vol.10 No.3, pp.179 - 193

Available online: 18 May 2017 *

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