Title: A partitioned instruction queue to reduce instruction wakeup energy

Authors: Marco A. Ramirez, Adrian Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa

Addresses: Computer Center for Research, National Polytechnic Institute of Mexico, Mexico. ' Computer Architecture Department, Polytechnic University of Catalonia, Spain. ' Computer Architecture Department, Polytechnic University of Catalonia, Spain. ' Department of Computer Science, University of California, Irvine, CA, USA. ' Computer Center for Research, National Polytechnic Institute of Mexico, Mexican Petroleum Institute, Mexico

Abstract: Instruction wakeup logic consumes a large amount of energy in out-of-order processors. Existing solutions to the problem require prediction or additional hardware complexity to reduce the energy consumption and, in some cases, may have a negative impact on processor performance. This paper proposes a new mechanism for instruction wakeup, which uses a partitioned instruction queue (IQ). The energy consumption of an IQ partition (block) is proportional to the number of entries in it. All the blocks are turned off until the mechanism determines which blocks to access on wakeup using a simple successor tracking mechanism. The proposed approach is shown to require as little as 1.5 comparisons per committed instruction for SPEC2000 benchmarks. The energy consumption and timing of the partitioned IQ design are evaluated using CACTI 3 models for a 0.07 µm process. The average energy savings observed were 85% and 92%, respectively, for 64-entry integer and floating-point partitioned IQs.

Keywords: superscalar processors; out-of-order execution; instruction window; instruction wakeup; low power; CAM; partitioned instruction queue; high performance computing; energy consumption.

DOI: 10.1504/IJHPCN.2004.008344

International Journal of High Performance Computing and Networking, 2004 Vol.1 No.4, pp.153 - 161

Available online: 07 Dec 2005 *

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