Authors: Jagannadha Naidu K; Kevin Kansagara; Harish M. Kittur
Addresses: VLSI Division, School of Electronics Engineering, VIT University, Vellore, India ' VLSI Division, School of Electronics Engineering, VIT University, Vellore, India ' VLSI Division, School of Electronics Engineering, VIT University, Vellore, India
Abstract: Electronic circuits in system on chip (SoC) require multiple stable voltages derived from power source available for chip. The proposed step-down converter design uses pulse frequency modulation with minimum number of transistors instead of high transistor density pulse width modulation and analogue to digital converter combination architecture to achieve high efficiency. This design is free from space-consuming inductor and adaptable to load changes as per supply voltage requirements of different power domains on a SoC. This design is implemented in 45 nm CMOS technology. The buck converter produces stable 0.3, 0.45, 0.6 and 0.8 V voltages with 1.2 V supply voltage and 500 MHz system clock frequency at load current of 100 µA.
Keywords: DC-DC converters; PFM; pulse frequency modulation; adaptive switched capacitor; voltage regulation; system on chip; SoC.
International Journal of Power Electronics, 2016 Vol.8 No.1, pp.38 - 51
Accepted: 28 Sep 2016
Published online: 25 Jan 2017 *