Authors: Zakaria Lakhdara; Salah Merniz
Addresses: LIRE Laboratory, Constantine 2 University, Constantine, Algeria ' MISC Laboratory, Constantine 2 University, Constantine, Algeria
Abstract: The increasing complexity of electronic systems requires a powerful abstraction and structuration mechanisms, as well as design methodologies that systematically and formally derives low-level concrete designs from high-level abstract ones. For this reason, in this research work, we present a methodological design approach that automatically generates a functional HDL code from SysML diagrams modelling hardware design. The generated HDL code is both verifiable and executable. While the first feature remains crucial for low-level design refinements, the second one enables design performance evaluation at early stages. In order to shed light on the features of the proposed approach, a case study is given. Specifically, it involves designing the micro-architecture of MIPS processor, generating its functional specification in CLEAN from its SysML model, and simulating it.
Keywords: digital circuit design; Unified Modelling Language; UML; SysML diagrams; CLEAN; functional programming; modelling; simulation; formal verification; HDL code generation; digital circuits.
International Journal of High Performance Systems Architecture, 2016 Vol.6 No.4, pp.222 - 237
Available online: 20 Jan 2017 *Full-text access for editors Access for subscribers Purchase this article Comment on this article