Title: Intelligent selective modular redundancy for online fault detection of adders in FPGA

Authors: Jisha M. Nair; C. Pradeep

Addresses: SAINTGITS College of Engineering, Pathamuttom, Kottayam, India ' Mar Baselios Christian College of Engineering and Technology (MBCCET), Pallikkunnu P.O., Kuttikkanam, Peermade, India

Abstract: Developments in VLSI technology have enabled single chip to perform complex functionalities. The increase in density of VLSI chip has necessitated online fault detection technique to increase reliability of digital systems. This paper proposes a data dependent technique of online fault detection for adder architectures. The type of data inputs to adder circuit are used efficiently to design an area optimised technique. The developed technique is capable of detecting single stuck-at faults that occur in an adder using two rail checker. A comparison is made by implementing the design in different FPGA devices. The results show that the proposed data path has better device utilisation and less delay in Virtex5. The technique has 28% area overhead when applied to carry select adders.

Keywords: defects; dual modular redundancy; DMR; errors; LUTs; look-up tables; modular redundancy; online fault detection; partial TMR; two rail checker; Virtex5; FPGA; field programmable gate arrays; adder architectures.

DOI: 10.1504/IJHPSA.2016.081756

International Journal of High Performance Systems Architecture, 2016 Vol.6 No.4, pp.213 - 221

Received: 30 Nov 2015
Accepted: 18 Jul 2016
Published online: 24 Jan 2017 *

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