Title: A compact model for electrostatic discharge protection nanoelectronics simulation

Authors: Hung-Mu Chou, Shao-Ming Yu, Jam-Wem Lee, Yiming Li

Addresses: Department of Communication Engineering and Microelectronics and Information Systems Research Center, National Chiao Tung University, Hsinchu 300, Taiwan. ' Department of Computer and Information Science and Microelectronics and Information Systems Research Center, National Chiao Tung University, Hsinchu 300, Taiwan. ' Microelectronics and Information Systems Research Center, National Chiao Tung University, Hsinchu 300, Taiwan. ' Department of Communication Engineering and Microelectronics and Information Systems Research Center, National Chiao Tung University, Hsinchu 300, Taiwan

Abstract: In nanoelectronics, snapback phenomena play an important role in electrostatic discharge (ESD) protection devices, in particular for gigascale, very large scale integration (VLSI) circuit design. In this paper we present a new ESD equivalent circuit model for deep submicrion and nanoscale semiconductor device simulation. By considering the geometry effect in the formulation of snapback characteristics, our model can be directly incorporated into electronic circuit simulation for the whole chip ESD protection circuit design. With the developed ESD model, we can investigate robust enhancement problems and perform a SPICE based whole chip ESD protection circuit design in nanoelectronics.

Keywords: geometry effect; ESD modelling; SPICE simulation; whole chip design; nanoelectronics; electrostatic discharge; circuit design.

DOI: 10.1504/IJNT.2005.008061

International Journal of Nanotechnology, 2005 Vol.2 No.3, pp.226 - 238

Available online: 11 Nov 2005 *

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