Title: Hardware support for early register release
Authors: Teresa Monreal, Víctor Vinals, Antonio Gonzalez, Mateo Valero
Addresses: Departamento de Informatica e Ingenieria de Sistemas, Universidad de Zaragoza HiPEAC network, Zaragoza, Spain. ' Departamento de Informatica e Ingenieria de Sistemas, Universidad de Zaragoza HiPEAC network, Zaragoza, Spain. ' Departament d'Arquitectura de Computadors, Universitat Politecnica de Catalunya, HiPEAC network, Barcelona, Spain. ' Departament d'Arquitectura de Computadors, Universitat Politecnica de Catalunya, HiPEAC network, Barcelona, Spain
Abstract: Register files are becoming one of the critical components of current out-of-order processors in terms of delay and power consumption, since their potential to exploit instruction-level parallelism is closely related to the size and number of ports of the register file. In conventional register-renaming schemes, register releasing is conservatively done only after the instruction that redefines the same register is committed. Instead, we propose a scheme that releases registers as soon as the processor knows that there will be no further use of them. We present two early releasing hardware implementations with different performance/complexity trade-offs. Detailed cycle-level simulations show either a significant speedup for a given register file size, or a reduction in register file size for a given performance level.
Keywords: register renaming; out-of-order processors; register files; optimisation; register releasing; precise exceptions.
DOI: 10.1504/IJHPCN.2005.008029
International Journal of High Performance Computing and Networking, 2005 Vol.3 No.2/3, pp.83 - 94
Published online: 10 Nov 2005 *
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