Title: Comprehensive investigation on array-type dummy active diffused region and gate geometries using narrow NMOSFETs with SiC S/D stressors

Authors: Chang-Chun Lee; Sen-Wen Cheng; Chia-Ping Hsieh; Ming-Han Liao; Yu-Huan Guo

Addresses: Department of Mechanical Engineering, National Chung Hsing University, 145 Xingda Rd., South Dist., Taichung City 402, Taiwan ' Department of Mechanical Engineering, Chung Yuan Christian University, 200 Chung Pei Road, Chung Li District, Taoyuan City, 32023, Taiwan ' Department of Mechanical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei 10617, Taiwan ' Department of Mechanical Engineering, National Taiwan University, No. 1, Sec. 4, Roosevelt Road, Taipei 10617, Taiwan ' Department of Mechanical Engineering, Chung Yuan Christian University, 200 Chung Pei Road, Chung Li District, Taoyuan City, 32023, Taiwan

Abstract: This study aims to investigate the combined strain effects of a dummy active diffused region (OD) and the salient gate width of a layout pattern on the mobility gain of a nanoscale device while considering the advanced stressors of a source/drain embedded silicon-carbon alloy with a 1.65% fraction mole of carbon and a contact etch stop layer with a tensile stress 1.0 GPa. To achieve this objective, we used a validated fabrication-oriented stress-simulated methodology to estimate the performance of a 22 nm n-type metal-oxide-semiconductor field-effect transistor. In addition, the important design factors of the device layout, including dummy OD width as well as the shallow trench isolation (STI) gap between the short channel device and the dummy OD, are parametrically analysed. Consequently, the mobility gains with different types of layout pattern considered in this study are acquired through the estimated relationship between the stress components of the device channel and silicon-based piezoresistance coefficients. The analytical results indicate that device performance improves depending on the layout pattern, such as the adoption of a small salient gate width, huge dummy OD regions, and a small STI gap.

Keywords: SiC stressors; silicon carbide; layout patterns; lattice mismatch strain engineering; stress simulation; mobility gain estimation; dummy active diffused region; gate geometries; narrow NMOSFETs; nanoscale device; nanotechnology; source-drain stressors; tensile stress; shallow trench isolation; piezoresistance coefficients; salient gate width.

DOI: 10.1504/IJNT.2016.078541

International Journal of Nanotechnology, 2016 Vol.13 No.7, pp.492 - 508

Available online: 17 Aug 2016 *

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