Title: VLSI architectures for high speed and low power implementation of 5/3 lifting discrete wavelet transform

Authors: N. Usha Bhanu; A. Chilambuchelvan

Addresses: Department of Electronics and Communication Engineering, SKR Engineering College, Anna University, Chennai-600123, Tamil Nadu, India ' Department of Electronics and Instrumentation Engineering, RMD Engineering College, Anna University, Chennai-601206, Tamil Nadu, India

Abstract: The inherent advantage of the in-place computation of the lifting-based discrete wavelet transform over the convolutional method makes it suitable for efficient hardware implementation with lower computational complexity. A high speed line-based direct mapped architecture for the lifting-based discrete wavelet of an image is proposed in this paper. Clock gating is used to reduce the switching activity of multipliers in the idle state for low power implementation of the lifting DWT. The comparison of the direct mapped and folded architectures is presented, in terms of speed and hardware requirements. The whole architecture is optimised to achieve better speed up and higher hardware utilisation by using a single clock for the predict and update operations. The speed performance of the folded architecture is limited by the critical path delay. The lifting algorithm is coded in MATLAB and implemented using Altera Cyclone II FPGA. The results obtained show that the hardware implementation of the lifting algorithm outperforms with respect to its software counterpart, achieving a high speed of 260 MHz, which is suitable for low power embedded multimedia applications.

Keywords: lifting-based DWT; VLSI architectures; clock gating; discrete wavelet transform; FPGA; field-programmable gate arrays; embedded multimedia.

DOI: 10.1504/IJCSE.2016.076213

International Journal of Computational Science and Engineering, 2016 Vol.12 No.2/3, pp.254 - 263

Received: 04 Nov 2012
Accepted: 16 May 2013

Published online: 28 Apr 2016 *

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