Title: Measuring the high performance of five-stage ring VCO with reverse body bias technique in 45 nm CMOS technology
Authors: Akansha Shrivastava; Anshul Saxena; Shyam Akashe
Addresses: Electronics & Communication Engineering Department, Pt. Devprabhakar Shastri College of Technology, Chhatarpur 471001, MP, India ' Electronics & Communication Engineering Department, Pt. Devprabhakar Shastri College of Technology, Chhatarpur 471001, MP, India ' Department of Electronics & Instrumentation, Institute of Technology and Management University, Gwalior 474001, MP, India
Abstract: In the CMOS, nanoscale technology power dissipation is becoming important metric. In presented work low leakage voltage controlled, ring systems oscillator circuit is proposed for critical communication systems with high oscillation frequency. An ideal approach has been investigated with substrate biasing technique for reduction of power consumption. We have shown simulation using cadence spectre 45 nm standard CMOS technology at room temperature (27°C) with supply voltage (Vdd=0.7 V). The simulation results provide efficient low power VCO in term of leakage power min (2.23 pW) and active power (9.03 nW) and max oscillation frequency (20.2 GHz) with joint PMOS and NMOS reverse substrate bias in comparison to PMOS and NMOS reverse substrate bias technique.
Keywords: VCO performance; voltage controlled oscillators; cadence virtuoso tool; leakage power; active power; oscillation frequency; five-stage ring VCOs; reverse body bias; CMOS technology; nanotechnology; power dissipation; substrate biasing; power consumption; simulation.
International Journal of Signal and Imaging Systems Engineering, 2016 Vol.9 No.2, pp.79 - 84
Received: 23 May 2013
Accepted: 17 Mar 2014
Published online: 23 Feb 2016 *