Title: A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults
Authors: Navya Mohan; J.P. Anita
Addresses: Department of ECE, Amrita Vishwa Vidyapeetham, India ' Department of ECE, Amrita Vishwa Vidyapeetham, India
Abstract: This paper presents a new zero suppressed binary decision diagram (ZBDD)-based approach for obtaining larger number of relaxed bits. These test sets find major application in reducing the power consumed during testing. Experiments performed on single and multiple stuck-at faults using ZBDDs show better results in terms of percentage of relaxation over the existing comparable BDD-based approaches. Moreover using these relaxed test vectors and by suitable X-filling methods average switching activity (ASA) of the circuit can be reduced, which will reduce the power dissipation during testing.
Keywords: zero suppressed binary decision diagrams; ZBDD; test power; test set relaxation; stuck-at faults; power consumption; average switching activity; circuit ASA; power dissipation.
International Journal of Mathematical Modelling and Numerical Optimisation, 2016 Vol.7 No.1, pp.83 - 96
Received: 31 Jan 2015
Accepted: 25 Aug 2015
Published online: 23 Jan 2016 *