Title: Design and analysis of RF-low power and low-phase noise CMOS ring oscillator for fully integrated RF communication systems technologies
Authors: Ashish Raman; Rakesh Kumar Sarin
Addresses: Department of Electronics and Communication Engineering, Dr. B R Ambedkar National Institute of Technology, Jalandhar, G T Road By – Pass, Punjab, Pin 144011, India ' Department of Electronics and Communication Engineering, Dr. B R Ambedkar National Institute of Technology, Jalandhar, G T Road By – Pass, Punjab, Pin 144011, India
Abstract: This manuscript presents the design and analysis of five-stage, low power ring oscillator. The ring oscillator has implemented in 0.18 µm CMOS one-poly six-metal-layer process technology and designed for frequency synthesiser module used in RF communication applications. This work uses a single ended topology and the delay cell is designed with both tail-ahead and tail-current concept for frequency improvement. This work projects the effect of transistor size (w/l) on the important parameters of oscillator viz. frequency and power dissipation. Measurements show that the oscillator covers a frequency range of 0.9-2 GHz. Their analyses demonstrate that the circuit consumes minimum power of 305 µW at 0.9 GHz and maximum 575 µW at 2 GHz oscillating frequency. The designed oscillator occupies an area of 296 * 130 µm² and manifest an improved phase noise level of −111.9 dBc/Hz.
Keywords: oscillator stability; CMOS; low power; phase noise; voltage controlled oscillator; VCO; ring oscillator design; VLSI; fine tuning; wireless communications; oscillator noise; PLL; RF communications; transistor size; frequency range; power dissipation; oscillating frequency; energy consumption.
International Journal of Information and Communication Technology, 2016 Vol.8 No.1, pp.79 - 94
Available online: 15 Dec 2015 *Full-text access for editors Access for subscribers Purchase this article Comment on this article