Title: Increased digitalisation of flash ADC in modern CMOS process: a review

Authors: Prachi Palsodkar; Pravin Dakhole

Addresses: Department of Electronics Engineering, Yeshwantrao Chavan College of Engineering, Nagpur, Maharastra, India ' Department of Electronics Engineering, Yeshwantrao Chavan College of Engineering, Nagpur, Maharastra, India

Abstract: Recent trends of flash ADC design demands low voltage, low power and high speed operation at low cost, which can achieve through system level, architecture and technology level changes. Traditional flash ADC with analogue comparators and passive elements, face high level of difficulty to meet this requirement. To overcome these sub-micron ADC design issues, a comparator and calibration unit digitalisation approach is adapted and implemented from last decade. In this paper, a brief survey is done on digitalised approach for modern day ADC designs. Threshold quantised comparators for 4 bit flash ADC designed and discussed here along with there performance parameters.

Keywords: digitalisation; threshold comparators; quantisation; calibration; transconductance; flash ADC design; analog-to-digital converters; CMOS.

DOI: 10.1504/IJCAD.2015.072623

International Journal of Circuits and Architecture Design, 2015 Vol.1 No.4, pp.355 - 368

Received: 15 Nov 2014
Accepted: 31 Mar 2015
Published online: 22 Oct 2015 *

Full-text access for editors Full-text access for subscribers Purchase this article Comment on this article