Title: Low-voltage gate and body driven self-biased cascode current mirror with enhanced bandwidth

Authors: Vandana Niranjan; Ashwani Kumar; Shail Bala Jain

Addresses: ECE Dept. IGDTUW, Guru Gobind Singh Indraprastha University, New Delhi, India ' ECE Dept. IGDTUW, Guru Gobind Singh Indraprastha University, New Delhi, India ' ECE Dept. IGDTUW, Guru Gobind Singh Indraprastha University, New Delhi, India

Abstract: In this paper, a new approach to enhance the bandwidth of self-biased cascode current mirror (SBCM) is explored. The proposed approach is based on gate and body driven technique. This technique boosts the transconductance in a MOS transistor as both gate and body/bulk terminals are tied together and used as signal input. This novel technique appears as a good solution to merge the advantages of gate-driven and bulk-driven techniques and suppress their disadvantages. The gate and body driven technique utilise body effect to enable low voltage operation by lowering the threshold voltage of MOS transistor and improves the overall circuit performance. The proposed technique achieves maximum bandwidth extension ratio of about two without compromising DC conditions. The proposed SBCM maintains high current copy accuracy due to improved output resistance and consumes only 131 µW. A small signal analysis validates the advantage of proposed bandwidth extension approach over previously reported approaches. The most attractive feature is design simplicity and complete elimination of any passive component or additional circuitry for bandwidth extension. Simulations in PSpice environment for 180 nm CMOS technology verified the predicted theoretical results. The proposed current mirror is particularly interesting for high frequency low noise analog signal processing and conditioning circuits.

Keywords: body effect; body bias; gate and body driven; bandwidth extension ratio; analogue signal processing; low voltage; low power; self-biased cascode current mirror; SBCM; transconductance; MOS transistors; circuit performance; circuit simulation.

DOI: 10.1504/IJCAD.2015.072615

International Journal of Circuits and Architecture Design, 2015 Vol.1 No.4, pp.320 - 342

Available online: 22 Oct 2015 *

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